The field of the invention is overlay measurements in manufacturing of semiconductor and similar devices formed from layers.
Modern semiconductor devices, such as integrated circuits, are typically fabricated from wafers of semiconductor material. The wafers are fabricated by a succession of patterned layers of semiconductor material. Circuit patterns are fabricated using a variety of long established techniques, for example, lithographic techniques.
Overlay metrology in semiconductor device fabrication is used to determine how well one printed layer is overlaid and aligned with a previously printed layer. Close alignment of each layer at all points within the device is important for reaching the design goals. It is consequently important for the efficiency of the manufacturing process that any alignment error between two patterned layers on a wafer can be measured quickly and accurately. It is similarly important to be able to measure any alignment error between successive exposures to the same layer. Misregistration between layers is referred to as overlay error. Overlay metrology tools or machines are used to measure the overlay error. This information may be fed into a closed loop system to correct the overlay error.
Current overlay metrology uses optically readable target marks or patterns printed onto layers of a substrate, typically a semiconductor wafer, during fabrication. The relative displacement of two successive layers is measured by imaging the patterns at high magnification, digitizing the images, and processing the image data using various known image analysis algorithms to quantify the overlay error. Overlay metrology techniques thus involve the direct measurement of misregistration between patterns provided in direct association with each of the layers. As semiconductor devices become progressively smaller, making accurate overlay measurements becomes increasingly difficult. It is also important that new measurement methods and systems be able to perform at the relatively high speeds achieved with existing overlay metrology technology. Use of repeated measurements is undesirable, unless they can be made without requiring significantly more time. Consequently, developing improved metrology methods and systems raises significant technical challenges.
One technique for working with increasingly smaller microelectronic devices is use of simple targets which can be reduced in size and placed within the active area of the device. U.S. patent application Ser. No. 11/035,652, incorporated herein by reference, describes these kinds of targets.
Targets which are small enough to be placed within the active area of devices allow measurements to be made where they are actually needed. Adoption of these targets requires that they be as small as practical and, ideally, that they can be measured with existing overlay tools. There is no single correct size for these targets. However, the smaller they are, the more likely they are to be used. Targets occupying an area of approximately 1 μm square are advantageously achieved. The “size” of the target must include any blank area around it required for proper measurement.
Current optical overlay measurement systems use visible light and operate with optical resolution of approximately 0.5-1.0 μm. These systems will generally not be able to resolve the features within the proposed targets. Although these types of systems may be changed to improve optical resolution, system changes tend to be relatively time consuming, costly and with potentially uncertain results. Consequently, changing the use and operation of existing systems to provide for accurate measurements of smaller targets would be highly advantageous.